In order to achieve advanced functions and performance improvement of semiconductor LSI, techniques for miniaturizing the wirings have been developed. For the further improvement in performance and reduction in power consumption, a technique in which a plurality of semiconductor chips equipped with LSI are stacked in three-dimensional directions to mount the chips in one package has attracted attention in recent years. Connection methods of the three-dimensional stacking include a wire bonding method and a flip chip method. In the wire bonding method, the position of pad electrodes on a chip is limited to the periphery of the chip, and when communication is to be carried out between stacked chips, the communication is always carried out via the pad electrodes formed in the vicinity of the outer edges of the chips. Therefore, the wiring length is increased, and there is a problem that wiring delay is increased. Moreover, since the number of provided pad electrodes is also limited, there is a problem that the transmission band is narrowed. On the other hand, in the flip chip method, connection by bumps formed on the entire surfaces of chips is possible, and the wiring length is short. However, the number of stacked chips is limited to two. As a three-dimensional connection method that solves these problems, there is a method in which stacked chips are electrically connected by using silicon through electrodes.
The connection method using the silicon through electrodes is a method in which many through holes are formed in a silicon substrate on which a semiconductor element has been formed, the through holes are filled with a conductor typified by copper, and the through holes filled with copper are used as electrodes to electrically connect stacked semiconductor chips to each other. When the plurality of chips provided with the silicon through electrodes are mutually connected, the chips can be connected at multiple points by the shortest distance, and there is no upper limit for the number of stacked semiconductor chips in principle.
Non-Patent Document 1 is an example of the three-dimensional connection method using the silicon through electrodes and is a method in which through holes are formed from a back surface of a semiconductor device having elements to bring them into contact with upper pads, thereby connecting them to a wiring layer. A typical conventional example of the three-dimensional connection method described in this document and problems thereof will be described with reference to FIG. 2 and FIG. 3.
First, the manufacturing process of the typical conventional example of a semiconductor device using the three-dimensional connection method using the silicon through electrodes will be shown. An under-wiring insulating film 200 made up of a silicon oxide film having a film thickness of 250 nm and silicon nitride having a film thickness of 50 nm is formed on a substrate 100 on which a semiconductor element has been formed, and a tungsten plug is formed in the under-wiring insulating film. Then, a first interlayer insulating film 201 using a Low-k material made of carbon-containing silicon oxide (SiOC) and having a film thickness of 100 nm is formed, and a first metal wiring 400 made of tantalum and copper is sequentially formed in the interlayer insulating film. Then, a first protective insulating film 204 made of nitrogen-containing silicon carbide (SiCN) and having a film thickness of 25 nm and a second interlayer insulating film 202 using a Low-k material made of SiOC and having a film thickness of 250 nm are sequentially formed, and parallel metal wirings 403A and 403B adjacent to a second metal wiring 401 made of tantalum and copper are formed in the interlayer insulating film. Then, a second protective insulating film 205 made of SiCN and having a film thickness of 25 nm and a third interlayer insulating film 203 using a Low-k material made of SiOC are sequentially formed, and a third metal wiring 402 made of tantalum and copper is formed in the interlayer insulating film 203. Then, a third protective insulating film 206 made of SiCN and having a film thickness of 25 nm is formed, an aluminum pad made up of a titanium nitride film having a film thickness of 50 nm and an aluminum film having a film thickness of 500 nm is formed, and a passivation film 207 made up of a silicon oxide film having a film thickness of 200 nm and a silicon nitride film having a film thickness of 250 nm is formed. Through the process described above, a semiconductor device having multilayer wirings can be formed.
Next, as shown in FIG. 3A, after a first back-surface insulating film 600 made of silicon oxide is formed by plasma CVD on the back surface of the substrate 100 on which the semiconductor element has been formed, an opening is provided by using lithography and dry etching in a region of the first back-surface insulating film 600 in which a silicon through electrode is desired to be formed, thereby forming a first back-surface insulating-film opening 700. Then, dry etching is carried out with using the back-surface insulating film as an etching mask until the etching penetrates through at least the substrate 100 on which the semiconductor device has been formed and reaches the first metal wiring 400, thereby forming a silicon through hole 701 as shown in FIG. 3B. Then, after a silicon oxide film having a film thickness of 1 μm is formed by plasma CVD so as to cover the silicon through hole 701, full-surface etch back is carried out to form a second back-surface insulating film 601 having a sidewall insulating film on the sidewall of the silicon through hole as shown in FIG. 3C. Then, a tantalum film having a film thickness of 50 nm and a plating seed film made of copper and having a film thickness of 50 nm are sequentially formed by using sputtering, and the silicon through hole 701 is completely filled with copper by using electrolytic plating. Thereafter, the tantalum film and the copper film in the region other than the silicon through hole 701 are removed by using chemical mechanical polishing, and a semiconductor device having a silicon through electrode 800 formed from the back surface of the substrate on which the semiconductor element has been formed is formed as shown in FIG. 3D. Hereinafter, the semiconductor device in which the silicon through electrode formed in accordance with the above-described process is formed will be referred to as a conventional example.
In the case in which the silicon through hole 701 having a depth of several tens μm that sufficiently penetrates through the silicon substrate and reaches the layer of the first metal wiring 400 having a thickness of 100 nm is to be formed by using dry etching as shown in FIG. 3B, the margin for the overetching is insufficient, and the etching proceeds to the first connection via layer or the metal wiring layer in the upper layer. If dry etching proceeds until the interlayer insulating film using the Low-k material and the silicon through hole are in contact with each other, the Low-k material is damaged by plasma. Furthermore, in a cleaning step after the dry etching step, the Low-k material absorbs moisture supplied in the cleaning. If the Low-k material absorbs moisture, since the dielectric constant of the interlayer insulating film made of the Low-k material increases, the parasitic capacitance of the metal wiring is increased, increase in wiring delay and power consumption occurs , and the circuit operation may be adversely affected.
Furthermore, the absorbed moisture may then oxidize the metal material constituting the metal wiring, which may cause the increase in the wiring resistance and conduction failure. In the process of forming the silicon through hole from the back surface of the substrate, a high-temperature process cannot be carried out unlike the pre-process. Therefore, there is a problem that it is difficult to return the Low-k material which has once absorbed moisture to the characteristics before the moisture absorption.